Design of Low-Voltage Digital Building Blocks and ADCs for Energy-Efficient Systems

Increasing number of energy-limited applications continue to drive the demand for designing systems with high energy efficiency. This tutorial covers the main building blocks of a system implementation including digital logic, embedded memories, and analog-to-digital converters and describes the challenges and solutions to designing these blocks for low-voltage operation

Energy-efficient system design for mobile processing platforms

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.Cataloged from PDF version of thesis.Includes bibliographical references (pages [189]-203).Portable electronics has fueled the rich emergence of multimedia applications that have led to the exponential growth in content creation and consumption. New energy-efficient integrated circuits and systems are necessary to enable the increasingly complex augmented-reality applications, such as high-performance multimedia, "big-data" processing and smart healthcare, in real-time on mobile platforms of the future. This thesis presents an energy-efficient system design approach with algorithm, architecture and circuit co-design for multiple application areas. A shared transform engine, capable of supporting multiple video coding standards in real-time with ultra-low power consumption, is developed. The transform engine, implemented using 45 nm CMOS technology, supports Quad Full-HD (4k x 2k) video coding with reconfigurable processing for H.264 and VC-1 standards at 0.5 V and operates down to 0.3 V to maximize energy-efficiency. Algorithmic and architectural optimizations, including matrix factorization, transpose memory elimination and data dependent processing, achieve significant savings in area and power consumption. A reconfigurable processor for computational photography is presented. An efficient implementation of the 3D bilateral grid structure supports a wide range of non-linear filtering applications, including high dynamic range imaging, low-light enhancement and glare reduction. The processor, implemented using 40 nm CMOS technology, enables real-time processing of HD images, while operating down to 0.5 V and achieving 280x higher energy-efficiency compared to software implementations on state-of-the-art mobile processors. A scalable architecture enables 8x energy scalability for the same throughput performance, while trading-off output resolution for energy. Widespread use of medical imaging techniques has been limited by factors such as size, weight, cost and complex user interface. A portable medical imaging platform for accurate objective quantification of skin condition progression, using robust computer vision techniques, is presented. Clinical validation shows 95% accuracy in progression assessment. Algorithmic optimizations, reducing the memory bandwidth and computational complexity by over 80%, pave the way for energy-efficient hardware implementation to enable real-time portable medical imaging.by Rahul Rithe.Ph. D

Statistical static timing analysis design methodology for low voltage operation

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Includes bibliographical references (p. [101]-103).Statistical process variations have long been an important design issue. But until recently, process variations have been global process variations, i.e., transistor parameters may vary from die to die but are constant within a die. With transistor geometries shrinking below 65nm, however, a new kind of statistical variation, known as Local or Intra-die variation, has become important for logic and memory. Local variations are primarily the result of variations in the number of dopant atoms in the channel of CMOS transistors. To achieve ultra-low power, ICs are being designed for VDD </- 0.5V. At these voltages, the stochastic delay resulting from local variations has standard deviation comparable to the nominal delay. In order to predict the statistical impact of local variations on circuit performance, it is necessary to develop the statistical models that accurately reflect local variations and to develop a computationally efficient algorithm for performing SSTA using these models. At low voltage (VDD </- 0.5V), circuit delay is a non-linear function of the transistor random variables. This greatly complicates the statistical analysis because the PDF of the circuit delay is non-Gaussian. Most of the current SSTA approaches that can handle non-Gaussian PDFs, have high computational complexities. In this work, a complete SSTA design methodology for local variations in logic timing at low voltage operation is presented. The approach can handle non-linear delays with non-Gaussian delay PDFs in a computationally efficient manner. The approach has been implemented using commercial CAD tools and integrated into commercially used IC design flow. Comparison with Monte-Carlo analysis demonstrates high accuracy of the approach.by Rahul Rithe.S.M

Guidance

1 Abstract

Reconfigurable processor for energy-scalable computational photography

Computational photography applications, such as lightfield photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging [3], Low-Light Enhanced (LLE) imaging [4], tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations [5] to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography

Reconfigurable Processor for Energy-Efficient Computational Photography

This paper presents an on-chip implementation of a scalable reconfigurable bilateral filtering processor for computational photography applications such as HDR imaging, low-light enhancement, and glare reduction. Careful pipelining and scheduling has minimized the local storage requirement to tens of kB. The 40-nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.5 V. The test chip processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared with software implementations on recent mobile processors

Reconfigurable processor for energy-scalable computational photography

Computational photography applications, such as lightfield photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photography. These techniques have a wide range of applications, including High-Dynamic Range (HDR) imaging [3], Low-Light Enhanced (LLE) imaging [4], tone management and video enhancement. The high computational complexity of such multimedia processing applications necessitates fast hardware implementations [5] to enable real-time processing. This paper describes a hardware implementation of a reconfigurable multi-application processor for computational photography